Invention Grant
- Patent Title: Patterned bit in error measurement apparatus and method
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Application No.: US15250617Application Date: 2016-08-29
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Publication No.: US10552252B2Publication Date: 2020-02-04
- Inventor: Jeon Seokhun , Oh Sungchul , Jung Pil-Woo , Jeong Seungyoul
- Applicant: Seagate Technology LLC
- Applicant Address: US CA Cupertino
- Assignee: SEAGATE TECHNOLOGY LLC
- Current Assignee: SEAGATE TECHNOLOGY LLC
- Current Assignee Address: US CA Cupertino
- Agency: Westman, Champlin & Koehler, P.A.
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/10 ; G11B20/18 ; G06F3/06 ; G11B7/095 ; G11B21/08 ; G11B20/12
Abstract:
A method includes detecting different data patterns in data read from a portion of a non-transitory data storage medium. Bit errors in the different data patterns are then determined. Further, bits in error for a total number of bits in each of the different data patterns are calculated from the determined bit errors in the different data patterns.
Public/Granted literature
- US20180060161A1 PATTERNED BIT IN ERROR MEASUREMENT APPARATUS AND METHOD Public/Granted day:2018-03-01
Information query
