An apparatus having an interface and a circuit is disclosed. The interface may be connectable to a plurality of counters and a plurality of chained pipelines. The circuit may be configured to (i) increment each of a plurality of counters associated with a data unit in a buffer in response to a request from a first pipeline of the chained pipelines to increment one of the counters. The first pipeline may generate the data unit in the buffer. A plurality of second pipelines of the chained pipelines may access the data in the buffer in response to the counters being incremented. The circuit may be further configured to (ii) receive a plurality of wake instructions from the counters and (iii) send another wake instruction to the first pipeline in response to reception of all of the wake instructions.