Invention Grant
- Patent Title: Forming stacked twin III-V nano-sheets using aspect-ratio trapping techniques
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Application No.: US15834721Application Date: 2017-12-07
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Publication No.: US10546928B2Publication Date: 2020-01-28
- Inventor: Pouya Hashemi , Karthik Balakrishnan , Alexander Reznicek , Mahmoud Khojasteh
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L33/00
- IPC: H01L33/00 ; H01L29/10 ; H01L29/06 ; H01L29/207 ; H01L29/34 ; H01L29/04 ; H01L21/02 ; H01L29/786 ; H01L29/66 ; H01L21/306
Abstract:
A semiconductor structure that includes: a substrate, a twin vertical punch-through stopper layer structure connected to the substrate, and a plurality of nanosheets connected to and supported by the twin vertical punch-through stopper structure and isolated from the substrate by an insulating dielectric.
Public/Granted literature
- US20190181228A1 FORMING STACKED TWIN III-V NANO-SHEETS USING ASPECT-RATIO TRAPPING TECHNIQUES Public/Granted day:2019-06-13
Information query
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