Invention Grant
- Patent Title: Resistive memory device having memory cell array and system including the same
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Application No.: US16195199Application Date: 2018-11-19
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Publication No.: US10546623B2Publication Date: 2020-01-28
- Inventor: Jaeho Lee , Jaeyoon Sim , Kyeongjun Lee
- Applicant: SAMSUNG ELECTRONICS CO., LTD. , POSTECH ACADEMY-INDUSTRY FOUNDATION
- Applicant Address: KR Suwon-si KR Pohang-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.,POSTECH ACADEMY-INDUSTRY FOUNDATION
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.,POSTECH ACADEMY-INDUSTRY FOUNDATION
- Current Assignee Address: KR Suwon-si KR Pohang-si
- Agency: Sughrue Mion, PLLC
- Priority: KR10-2018-0045743 20180419
- Main IPC: G11C11/16
- IPC: G11C11/16 ; G11C11/54

Abstract:
A resistive memory device includes a memory cell array in which a plurality of memory cells are arranged. Each of the plurality of memory cells includes a variable resistor comprising a first end connected to a bit line, and a second end, a row transistor connected between a row source line and the second end of the variable resistor, the row transistor being selectable by a row word line, and a column transistor connected between a column source line and the second end of the variable resistor, the column transistor being selectable by a column word line. Based on the row transistor being selected, first data is written or second data is read in a row direction of the memory cell array, and based on the column transistor being selected, the first data is written or the second data is read in a column direction of the memory cell array.
Public/Granted literature
- US20190325933A1 RESISTIVE MEMORY DEVICE HAVING MEMORY CELL ARRAY AND SYSTEM INCLUDING THE SAME Public/Granted day:2019-10-24
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