A circuit includes a clock generator configured to generate a first latching clock signal and a second latching clock signal. Responsive to a select signal, one of the first latching clock signal or the second latching clock signal has a clock signal frequency and the other of the first latching clock signal or the second latching clock signal has a predetermined logic value. A multiplexing latch circuit is configured to select either first data on a first data line or second data on a second data line based on the first latching clock signal and the second latching clock signal.