Invention Grant
- Patent Title: Input/output circuit
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Application No.: US16202012Application Date: 2018-11-27
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Publication No.: US10541684B2Publication Date: 2020-01-21
- Inventor: Katsuyoshi Yagi
- Applicant: LAPIS SEMICONDUCTOR CO., LTD.
- Applicant Address: JP Yokohama
- Assignee: LAPIS SEMICONDUCTOR CO., LTD.
- Current Assignee: LAPIS SEMICONDUCTOR CO., LTD.
- Current Assignee Address: JP Yokohama
- Agency: Volentine, Whitt & Francos, PLLC
- Priority: JP2017-227457 20171128
- Main IPC: H03K19/003
- IPC: H03K19/003 ; H03K17/687 ; H03K19/00

Abstract:
An input/output circuit including: a first transistor that, based on an input signal and an enable signal input to an enable terminal that switches a validity and invalidity of an output, drives a load connected between an output terminal and an external power supply; a first switch provided between the input terminal and a control terminal of the first transistor, and including a first switching terminal that switches between connecting or blocking the input signal; and a switch control section that controls the first switching terminal based on the enable signal, wherein, when a logic of the enable signal has transitioned, the switch control section controls the first switching terminal to cause the first switch to be in a connecting state for a predetermined period, to input the input signal to the control terminal of the first transistor, and to suppress a current flowing to the load.
Public/Granted literature
- US20190165785A1 INPUT/OUTPUT CIRCUIT Public/Granted day:2019-05-30
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