A method for fabricating a semiconductor device includes providing a base substrate, forming a plurality of doped regions in the base substrate, forming an initial capping layer covering surfaces of the plurality of doped regions, forming a dielectric layer on the initial capping layer and the base substrate, forming a plurality of vias in the dielectric layer to expose a surface portion of the initial capping layer, and etching the exposed surface portion of the initial capping layer at a bottom of each via to form a silicide region exposed at the bottom of the via. The silicide region has a reduced thickness compared with a thickness of the initial capping layer. The method further includes forming a metal silicide layer by performing a self-aligned silicide process on an entire silicide region. The metal silicide layer is in contact with the plurality of doped regions.