- Patent Title: High Electron Mobility Transistor with dual thickness barrier layer
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Application No.: US15913068Application Date: 2018-03-06
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Publication No.: US10541313B2Publication Date: 2020-01-21
- Inventor: Gilberto Curatola , Oliver Haeberlen
- Applicant: Infineon Technologies Austria AG
- Applicant Address: AT Villach
- Assignee: Infineon Technologies Austria AG
- Current Assignee: Infineon Technologies Austria AG
- Current Assignee Address: AT Villach
- Agency: Murphy, Bilak & Homiller, PLLC
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/66 ; H01L29/778 ; H01L29/417 ; H01L29/20 ; H01L29/10

Abstract:
A method of forming a semiconductor device includes providing a heterojunction semiconductor body. The heterojunction semiconductor body includes a first type III-V semiconductor layer and a second type III-V semiconductor layer formed over the first type III-V semiconductor layer. The second type III-V semiconductor layer has a different bandgap as the first type III-V semiconductor layer such that a first two-dimensional charge carrier gas forms at an interface between the first and second type III-V semiconductor layers. The second type III-V semiconductor layer has a thicker section and a thinner section. A first input-output electrode is formed on the thicker section. A gate structure and a second input-output are formed on the thinner section. The gate structure is laterally spaced apart from a transition between the thicker and thinner sections of the second type III-V semiconductor layer.
Public/Granted literature
- US20190280100A1 High Electron Mobility Transistor with Dual Thickness Barrier Layer Public/Granted day:2019-09-12
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