Invention Grant
- Patent Title: Three-dimensional semiconductor memory device including slit with lateral surfaces having periodicity
-
Application No.: US16042424Application Date: 2018-07-23
-
Publication No.: US10541251B2Publication Date: 2020-01-21
- Inventor: Genki Kawaguchi , Masanari Fujita , Hideki Inokuma , Osamu Matsuura , Takeshi Imamura , Hideo Wada , Makoto Watanabe , Hajime Kaneko , Kenichi Fujii , Takanobu Itoh
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L29/792
- IPC: H01L29/792 ; H01L27/11582 ; H01L27/11565
Abstract:
According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N−2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.
Public/Granted literature
- US20180350834A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE INCLUDING SLIT WITH LATERAL SURFACES HAVING PERIODICITY Public/Granted day:2018-12-06
Information query
IPC分类:
