Invention Grant
- Patent Title: Semiconductor device having stacked chips
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Application No.: US16184993Application Date: 2018-11-08
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Publication No.: US10541231B2Publication Date: 2020-01-21
- Inventor: Masaru Koyanagi
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz & Volek PC
- Priority: JP2012-196392 20120906
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H03K99/00 ; G11C5/06 ; G11C8/12 ; H01L23/00 ; G11C29/00 ; G06F3/06 ; G11C16/08 ; H01L23/48 ; H01L23/50 ; G11C16/04

Abstract:
A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.
Public/Granted literature
- US20190096854A1 SEMICONDUCTOR DEVICE HAVING STACKED CHIPS Public/Granted day:2019-03-28
Information query
IPC分类: