Invention Grant
- Patent Title: Partial block memory operations
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Application No.: US13564458Application Date: 2012-08-01
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Publication No.: US10541029B2Publication Date: 2020-01-21
- Inventor: Peter Sean Feeley , Koji Sakui , Akira Goda
- Applicant: Peter Sean Feeley , Koji Sakui , Akira Goda
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G11C16/08
- IPC: G11C16/08 ; G11C16/04 ; G11C16/10 ; G11C16/16

Abstract:
Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.
Public/Granted literature
- US20140036590A1 PARTIAL BLOCK MEMORY OPERATIONS Public/Granted day:2014-02-06
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