Invention Grant
- Patent Title: Ternary content addressable memory wiring arrangement
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Application No.: US16030136Application Date: 2018-07-09
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Publication No.: US10541028B2Publication Date: 2020-01-21
- Inventor: Makoto Yabuuchi
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2017-152780 20170807
- Main IPC: G11C15/04
- IPC: G11C15/04 ; H01L23/528 ; H01L23/552 ; H01L27/088 ; H01L27/105 ; G11C8/08

Abstract:
A semiconductor storage device includes: a first memory cell joined to first and second word lines and a first match line; and a second memory cell joined to the first and second word lines and a second match line. The first and second memory cells are arranged adjacent to each other in planar view, and the first and second word lines are formed using wirings of a first wiring layer. The first and second match lines are formed using wirings of a second wiring layer provided adjacent to the first wiring layer. The first and second word lines are provided in parallel with each other between two first wirings to which a first reference potential is supplied. The first and second match lines are provided in parallel with each other between two second wirings to which the first reference potential is supplied.
Public/Granted literature
- US20190043582A1 SEMICONDUCTOR STORAGE DEVICE Public/Granted day:2019-02-07
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