Invention Grant
- Patent Title: Apparatus and method for bonding branch instruction with architectural delay slot
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Application No.: US13789467Application Date: 2013-03-07
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Publication No.: US10540179B2Publication Date: 2020-01-21
- Inventor: Ranganathan Sudhakar , Parthiv Pota
- Applicant: MIPS Tech, LLC
- Applicant Address: US CA Campbell
- Assignee: MIPS Tech, LLC
- Current Assignee: MIPS Tech, LLC
- Current Assignee Address: US CA Campbell
- Agency: Adam Intellex, PLC
- Main IPC: G06F9/30
- IPC: G06F9/30
Abstract:
A processor is configured to identify a branch instruction immediately followed by an architectural delay slot. A single bonded instruction comprising the branch instruction immediately followed by the architectural delay slot is created. The single bonded instruction is loaded into an instruction buffer.
Public/Granted literature
- US20140258694A1 Apparatus and Method for Branch Instruction Bonding Public/Granted day:2014-09-11
Information query
