Invention Grant
- Patent Title: Concurrent I/O enclosure firmware/field-programmable gate array (FPGA) update in a multi-node environment
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Application No.: US16128920Application Date: 2018-09-12
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Publication No.: US10540170B2Publication Date: 2020-01-21
- Inventor: Gary W. Batchelor , Veronica S. Davila , Enrique Q. Garcia , Robin Han , Jay T. Kirch , Ronald D. Martens , Trung N. Nguyen , Brian A. Rinaldi , Todd C. Sorenson
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Konrad Raynes Davda & Victor LLP
- Agent Janaki K. Davda
- Main IPC: G06F9/44
- IPC: G06F9/44 ; G06F8/65 ; H04L29/08

Abstract:
Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.
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