The present disclosure relates to a pixel compensation circuit and display device. The circuit includes: first to fifth switching elements, a storage capacitor, and a driving element. Each of the first to fifth switching elements and the driving element has a control terminal, a first terminal and a second terminal. The storage capacitor has first and second terminals. The control terminals of the first and second switching elements are coupled to an output terminal for outputting an n-th gate driving signal, the control terminals of the third and fourth switching elements are coupled to an output terminal for outputting an enabling signal, the control terminal of the fifth switching element is coupled to an output terminal for outputting an (n−1)-th gate driving signal, the control terminal of the driving element is coupled to the second node, and the storage capacitor is coupled between the first and second nodes.