One or more hardware components identify a bottleneck stage within a processor pipeline that processes frames of a video stream. The bottleneck stage has a first clock. An upstream stage receives a feedback signal from the bottleneck stage. The upstream stage has a second clock and the feedback signal includes information as to time required by the bottleneck stage to operate on data and information as to time the data spent queued. The upstream stage adjusts the speed at which the upstream stage operates and queues data to approximate the speed at which the bottleneck stage is operating and queuing data.