The present invention provides a high-frequency delay-locked loop and a clock processing method for the high-frequency delay-locked loop. The high-frequency delay-locked loop comprises a DLL circuit and a DCC circuit that are sequentially connected in series, and a pulse generating circuit used for generating a clock having a fixed pulse width. The fixed pulse width is a high-level width of the clock having the fixed pulse width and not smaller than a minimum pulse width required by the DLL circuit. The fixed pulse width enables a low-level width of the clock having the fixed pulse width to be not smaller than the minimum pulse width required by the DLL circuit. The clock having the fixed pulse width is input into the DLL circuit.