Invention Grant
- Patent Title: Vertical metal oxide semiconductor transistor
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Application No.: US16140551Application Date: 2018-09-25
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Publication No.: US10403758B2Publication Date: 2019-09-03
- Inventor: Ching-Wen Hung
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Priority: CN201710816267 20170912
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/66 ; H01L21/768 ; H01L23/535 ; H01L23/532 ; H01L29/06 ; H01L29/423
Abstract:
A vertical MOS transistor includes a substrate having therein a first source/drain region and a first ILD layer. A nanowire is disposed in the first ILD layer. A lower end of the nanowire is in direct contact with the first source/drain region, and an upper end of the nanowire is coupled with a second source/drain region. The second source/drain region includes a conductive layer. A gate electrode is disposed in the first ILD layer. The gate electrode surrounds the nanowire. A contact hole is disposed in the first ILD layer. The contact hole exposes a portion of the first source/drain region. A contact plug is disposed in the contact hole. A second ILD layer covers the first ILD layer.
Public/Granted literature
- US20190081181A1 VERTICAL METAL OXIDE SEMICONDUCTOR TRANSISTOR Public/Granted day:2019-03-14
Information query
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