Invention Grant
- Patent Title: Gate planarity for FinFET using dummy polish stop
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Application No.: US15471693Application Date: 2017-03-28
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Publication No.: US10403740B2Publication Date: 2019-09-03
- Inventor: Veeraraghavan S. Basker , Kangguo Cheng , Theodorus E. Standaert , Junli Wang
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L21/3105 ; H01L27/088 ; H01L29/06 ; H01L29/423 ; H01L29/66 ; H01L21/762 ; H01L27/12 ; H01L21/84 ; H01L21/8234 ; H01L21/321

Abstract:
A method for forming a semiconductor device includes depositing a dielectric layer over fins formed in a semiconductor substrate. The dielectric layer includes a screen layer over tops of the fins. An etch stop feature is formed on the screen layer. The etch stop feature is patterned down to the screen layer in regions across the device. A dummy gate material formed over the fins is planarized down to the etch stop feature, a dielectric fill between gate structures patterned from the dummy gate material is planarized down to the etch stop feature and a gate conductor is planarized to the etch stop feature.
Public/Granted literature
- US20170200714A1 GATE PLANARITY FOR FINFET USING DUMMY POLISH STOP Public/Granted day:2017-07-13
Information query
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