- Patent Title: Combined gate trench and contact etch process and related structure
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Application No.: US15171164Application Date: 2016-06-02
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Publication No.: US10403712B2Publication Date: 2019-09-03
- Inventor: Ling Ma
- Applicant: Infineon Technologies Americas Corp.
- Applicant Address: US CA El Segundo
- Assignee: Infineon Technologies Americas Corp.
- Current Assignee: Infineon Technologies Americas Corp.
- Current Assignee Address: US CA El Segundo
- Agency: Murphy, Bilak & Homiller, PLLC
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/10 ; H01L29/66 ; H01L29/49 ; H01L29/78 ; H01L29/739 ; H01L29/45

Abstract:
A method of forming a semiconductor device, the method comprises forming a gate trench and a contact trench concurrently in a semiconductor substrate using a patterned masking layer, forming a gate conductive filler in the gate trench, forming a deep body region below the contact trench, and forming a contact conductive filler in the contact trench. The method further comprises forming a gate trench dielectric liner in the gate trench, forming a gate trench dielectric liner in the gate trench, and forming an interlayer dielectric layer (IDL) over the gate conductive filler. The method further comprises forming a contact implant at a bottom of the contact trench, and forming a barrier layer in the contact trench.
Public/Granted literature
- US20170352723A1 Combined Gate Trench and Contact Etch Process and Related Structure Public/Granted day:2017-12-07
Information query
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