Various implementations described herein are directed to an integrated circuit having multiple access wires including a first access wire coupled to a first access port of the integrated circuit and a second access wire coupled to a second access port of the integrated circuit. The integrated circuit may include inverter circuitry having a first plurality of inverters coupled to the first access wire and a second plurality of inverters coupled to the second access wire. The first plurality of inverters may be positioned adjacent to the second plurality of inverters in an alternating manner.