- Patent Title: Semiconductor device having an anti-fuse element and method for suppressing the expansion of the cell current distribution to improve the writing yield thereof
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Application No.: US15631263Application Date: 2017-06-23
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Publication No.: US10403380B2Publication Date: 2019-09-03
- Inventor: Hiromichi Takaoka
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONCIS CORPORATION
- Current Assignee: RENESAS ELECTRONCIS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2016-130389 20160630
- Main IPC: G11C17/16
- IPC: G11C17/16 ; G11C17/18 ; H01L23/525 ; H01L23/528 ; H01L27/112 ; H01L29/06

Abstract:
A semiconductor device with an anti-fuse element includes a semiconductor substrate, a well region of a first conductivity type formed in the semiconductor substrate, and a gate electrode formed over the semiconductor substrate through a gate insulating film, and source regions of a second conductivity type opposite to the first conductivity type formed within the well region at the both ends of the gate electrode. When writing in the fuse element, a first writing potential is applied to the gate electrode, a first reference potential is applied to the well region, an intermediate potential is supplied to the source regions, and the intermediate potential is lower than the first writing potential and higher than the first reference potential.
Public/Granted literature
- US20180005704A1 SEMICONDUCTOR DEVICE Public/Granted day:2018-01-04
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