Invention Grant
- Patent Title: Reduction of output voltage ripple in booster circuit
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Application No.: US16131770Application Date: 2018-09-14
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Publication No.: US10403374B2Publication Date: 2019-09-03
- Inventor: Takeshi Hioka
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Kim & Stewart LLP
- Priority: JP2016-128774 20160629
- Main IPC: G11C5/04
- IPC: G11C5/04 ; G11C16/30 ; G11C16/04 ; G11C16/32 ; H02M3/07 ; G11C7/10 ; G11C16/08 ; G11C16/26

Abstract:
A booster circuit includes a charge pump circuit and a clock processing circuit. The clock processing circuit includes a first transistor of a first conductivity type, a second transistor of a second conductivity type, and a third transistor of a third conductivity type. The first and second transistors are connected in series between a high-voltage node and a low-voltage node, and gates of the first and second transistors are connected to each other. The third transistor is connected in parallel with the first transistor between the high-voltage node and an output terminal of the clock processing circuit that is connected to a node between the first transistor and the second transistor and to the charge pump circuit.
Public/Granted literature
- US20190027226A1 BOOSTER CIRCUIT Public/Granted day:2019-01-24
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