Invention Grant
- Patent Title: Data lane validation procedure for multilane protocols
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Application No.: US16201369Application Date: 2018-11-27
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Publication No.: US10402365B2Publication Date: 2019-09-03
- Inventor: Radu Pitigoi-Aron , Lalan Jee Mishra , Richard Dominic Wietfeldt
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza LLP
- Main IPC: G06F13/42
- IPC: G06F13/42 ; G06F13/364 ; H04L5/00

Abstract:
Systems, methods, and apparatus are described that enable a serial bus to be operated in multiple modes that employ additional wires for communicating data such that the bus width may be dynamically extended to improve bandwidth and/or throughput. One method includes transmitting a set of frames or sequences of symbols configured to carry up to a maximum number of data bytes over the serial bus, transmitting control signaling over a first data lane and the clock lane after the set of frames or sequences of symbols has been transmitted, and transmitting a first signal over a second data lane while transmitting the control signaling that may indicate whether the set of frames or sequences of symbols includes padding. The first signal may indicate a number of valid bytes or words in the set of frames or sequences of symbols.
Public/Granted literature
- US20190220436A1 DATA LANE VALIDATION PROCEDURE FOR MULTILANE PROTOCOLS Public/Granted day:2019-07-18
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