Invention Grant
- Patent Title: Digital phase locked loop
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Application No.: US15779119Application Date: 2016-11-10
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Publication No.: US10382046B2Publication Date: 2019-08-13
- Inventor: Chang Sik Yoo
- Applicant: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
- Applicant Address: KR Seoul
- Assignee: Industry-University Cooperation Foundation Hanyang University
- Current Assignee: Industry-University Cooperation Foundation Hanyang University
- Current Assignee Address: KR Seoul
- Agency: Sughrue Mion, PLLC
- Priority: KR10-2015-0175097 20151209
- International Application: PCT/KR2016/012911 WO 20161110
- International Announcement: WO2017/099368 WO 20170615
- Main IPC: G04F10/00
- IPC: G04F10/00 ; H03L7/089 ; H03L7/093 ; H03L7/099

Abstract:
A digital phase locked loop realizing high bandwidth is disclosed. The digital locked loop generates a first digital code corresponding to a difference between a rising edge of a reference signal and a rising edge of a feedback signal and a second digital code corresponding to a difference between a falling edge of the reference signal and a falling edges of the feedback signal, generates a third digital code by adding the first digital code and the second digital code, generates a first frequency control code at the rising edge of the reference signal and a second frequency control code at the falling edge of the reference signal by filtering the third digital code, outputs a specific frequency depending on the first frequency control code and the second frequency control code.
Public/Granted literature
- US20180351562A1 DIGITAL PHASE LOCKED LOOP Public/Granted day:2018-12-06
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