Integrated circuits with electrostatic discharge (ESD) protection and methods of providing ESD protection in an integrated circuit are provided. An ESD protection circuit the ESD protection circuit may incorporate a transistor, such as a MOSFET, and a voltage limiter coupled to a gate of the transistor. The voltage limiter may be configured such that with an ESD disturbance on the voltage supply rail, Vdd, a gate voltage of the transistor of the ESD protection circuit is held below the supply voltage (Vdd) inducing base current, Isub, within the transistor to effectively shunt a current arising from the ESD event from the voltage supply rail Vdd to the voltage supply rail Vss.