Invention Grant
- Patent Title: Method of manufacturing semiconductor device and semiconductor device
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Application No.: US15798369Application Date: 2017-10-30
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Publication No.: US10381279B2Publication Date: 2019-08-13
- Inventor: Akira Yajima
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2015-168248 20150827
- Main IPC: H01L21/66
- IPC: H01L21/66 ; G11C29/48 ; H01L25/065 ; H01L21/324 ; H01L21/4763 ; G11C29/06 ; H01L23/00 ; H01L23/31 ; G11C29/56

Abstract:
To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring.
Public/Granted literature
- US20180068910A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE Public/Granted day:2018-03-08
Information query
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