Invention Grant
- Patent Title: Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers
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Application No.: US15984586Application Date: 2018-05-21
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Publication No.: US10381261B2Publication Date: 2019-08-13
- Inventor: Igor Peidous , Jeffrey L. Libbert , Srikanth Kommu , Andrew Marquis Jones , Samuel Christopher Pratt , Horacio Josue Mendez , Leslie George Stanton , Michelle Rene Dickinson
- Applicant: SunEdison Semiconductor Limited (UEN201334164H)
- Applicant Address: TW Hsinchu
- Assignee: GlobalWafers Co., Ltd.
- Current Assignee: GlobalWafers Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Armstrong Teasdale LLP
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/02
Abstract:
A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.
Public/Granted literature
- US20180277421A1 METHOD OF MANUFACTURING HIGH RESISTIVITY SEMICONDUCTOR-ON-INSULATOR WAFERS WITH CHARGE TRAPPING LAYERS Public/Granted day:2018-09-27
Information query
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