A system for a backplane serializer/deserializer (SerDes) including first and second integrated circuits (IC). The first and second ICs include transmitters and receivers coupled to each other through first and second bidirectional links. A first receiver is configured to receive first data at a data rate on a first channel supported by both the first bidirectional link and the second bidirectional link. A second receiver is configured to receive second data at the data rate on a second channel supported by both the first bidirectional link and the second bidirectional link. The backplane SerDes is configured to transfer the first and second data in full duplex mode by employing two-bit pulse-amplitude modulation (PAM-4) to reduce signaling speed of the first and second bidirectional links without reducing throughput of a lane pair including the first and second channels.