- Patent Title: Low power retention flip-flop with level-sensitive scan circuitry
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Application No.: US15916130Application Date: 2018-03-08
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Publication No.: US10374584B1Publication Date: 2019-08-06
- Inventor: Charles Augustine , Muhammad Khellah , Arvind Raman , Feroze Merchant , Ashish Choubal
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- Main IPC: H03K3/037
- IPC: H03K3/037 ; G01R31/3185

Abstract:
An apparatus comprising: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail.
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