Invention Grant
- Patent Title: Vertical fin field effect transistor with reduced gate length variations
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Application No.: US15873564Application Date: 2018-01-17
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Publication No.: US10374083B1Publication Date: 2019-08-06
- Inventor: Chen Zhang , Kangguo Cheng , Xin Miao , Wenyu Xu
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L29/78 ; H01L21/8234 ; H01L21/762 ; H01L21/311 ; H01L29/10 ; H01L21/3065 ; H01L29/66 ; H01L29/06 ; H01L29/423 ; H01L29/08

Abstract:
A method of forming a fin field effect transistor is provided. The method includes forming an elevated substrate tier on a substrate, and forming a fin mesa on the elevated substrate tier with a fin template layer on the fin mesa, wherein the elevated substrate tier is laterally larger than the fin mesa and fin template layer. The method includes forming a fill layer on the substrate, wherein the fill layer surrounds the fin mesa, elevated substrate tier, and fin template layer, forming a plurality of fin masks on the fill layer and fin template layer, and removing portions of the fill layer, fin template layer, and fin mesa to form a plurality of dummy fins from the fill layer, one or more vertical fins from the fin mesa, and a dummy fin portion on opposite ends of each of the one or more vertical fins from the fill layer.
Public/Granted literature
- US20190221667A1 VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED GATE LENGTH VARIATIONS Public/Granted day:2019-07-18
Information query
IPC分类: