Invention Grant
- Patent Title: In-design real-time electrical impact verification flow
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Application No.: US14843982Application Date: 2015-09-02
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Publication No.: US10372867B2Publication Date: 2019-08-06
- Inventor: Jun Wang , Randy Bishop , Jingyu Xu , Dick Liu , Hu Cai , Jun Lu
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: SYNOPSYS, INC.
- Current Assignee: SYNOPSYS, INC.
- Current Assignee Address: US CA Mountain View
- Agency: Alston & Bird LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455

Abstract:
Techniques for analyzing a routed interconnection of a net of a circuit are discussed herein. Some embodiments may include a method comprising with a computer, analyzing the circuit to determine a performance parameter of the net, wherein the circuit is analyzed based at least in part on applying pre-layout simulation data of the net to layout data of the circuit. Additionally or alternatively, the circuit may be analyzed based on extracting characteristics of the routed interconnection from the layout data of the net.
Public/Granted literature
- US20170249415A9 IN-DESIGN REAL-TIME ELECTRICAL IMPACT VERIFICATION FLOW Public/Granted day:2017-08-31
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