Invention Grant
- Patent Title: Packed data operation mask concatenation processors, methods, systems, and instructions
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Application No.: US15442823Application Date: 2017-02-27
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Publication No.: US10372449B2Publication Date: 2019-08-06
- Inventor: Bret L. Toll , Robert Valentine , Jesus Corbal San Andrian , Elmoustapha Ould-Ahmed-Vall , Mark J. Charney
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: NDWE, LLP
- Main IPC: G06F15/00
- IPC: G06F15/00 ; G06F15/76 ; G06F9/30

Abstract:
A method of an aspect includes receiving a packed data operation mask concatenation instruction. The packed data operation mask concatenation instruction indicates a first source having a first packed data operation mask, indicates a second source having a second packed data operation mask, and indicates a destination. A result is stored in the destination in response to the packed data operation mask concatenation instruction. The result includes the first packed data operation mask concatenated with the second packed data operation mask. Other methods, apparatus, systems, and instructions are disclosed.
Public/Granted literature
- US20170300327A1 PACKED DATA OPERATION MASK CONCATENATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS Public/Granted day:2017-10-19
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