Invention Grant
- Patent Title: Configurable intra coding performance enhancements
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Application No.: US14857633Application Date: 2015-09-17
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Publication No.: US10341664B2Publication Date: 2019-07-02
- Inventor: Jason Tanner
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- Main IPC: H04N19/103
- IPC: H04N19/103 ; H04N19/105 ; H04N19/107 ; H04N19/109 ; H04N19/11 ; H04N19/156 ; H04N19/159 ; H04N19/176 ; H04N19/137

Abstract:
Techniques related to intra coding performance enhancements discussed. Such techniques may include determining intra coding modes based in part on processing performance costs associated with available intra modes and/or generating a block encode order based on intra coding modes, performing encoding, and re-ordering the encoded blocks to a default coding order for bitstream insertion.
Public/Granted literature
- US20170085885A1 CONFIGURABLE INTRA CODING PERFORMANCE ENHANCEMENTS Public/Granted day:2017-03-23
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