Invention Grant
- Patent Title: Method for increasing the integration level of superconducting electronics circuits, and a resulting circuit
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Application No.: US15679935Application Date: 2017-08-17
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Publication No.: US10283694B2Publication Date: 2019-05-07
- Inventor: Daniel Yohannes , Alexander F. Kirichenko , John Vivalda , Richard Hunt
- Applicant: Hypres, Inc.
- Applicant Address: US NY Elmsford
- Assignee: Hypres, Inc.
- Current Assignee: Hypres, Inc.
- Current Assignee Address: US NY Elmsford
- Agency: Tully Rinckey PLLC
- Agent Steven M. Hoffberg
- Main IPC: H01L39/22
- IPC: H01L39/22 ; H01L27/18 ; H01L39/24 ; H01L39/02 ; G11C11/44

Abstract:
A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.
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