Invention Grant
- Patent Title: Method of manufacturing semiconductor device
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Application No.: US15917607Application Date: 2018-03-10
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Publication No.: US10283527B2Publication Date: 2019-05-07
- Inventor: Yoshiki Yamamoto
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Priority: JP2017-105973 20170529
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L21/84 ; H01L29/66 ; H01L21/265 ; H01L29/423 ; H01L21/225 ; H01L29/78 ; H01L29/167 ; H01L21/324 ; H01L21/8234 ; H01L21/8238

Abstract:
An SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer is provided. A first region is one for forming a low breakdown voltage MISFET in the semiconductor layer, and a second region, in which the insulating layer and the semiconductor layer have been removed, is one for forming a high breakdown voltage MISFET. After an n-type semiconductor region is formed in the second region and an n-type extension region is formed in the first region, a first heat treatment is performed on the semiconductor substrate. Thereafter, a diffusion layer is formed in each of the first and second regions, and then a second heat treatment is performed on the semiconductor substrate. Herein, the time for which the first heat treatment is performed is longer than the time for which the second heat treatment is performed.
Public/Granted literature
- US20180342537A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2018-11-29
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