Invention Grant
- Patent Title: Molding structure for wafer level package
-
Application No.: US15911281Application Date: 2018-03-05
-
Publication No.: US10283427B2Publication Date: 2019-05-07
- Inventor: Chen-Hua Yu , Chung-Shi Liu , Chih-Fan Huang , Chih-Wei Lin , Wei-Hung Lin , Ming-Da Cheng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company
- Current Assignee: Taiwan Semiconductor Manufacturing Company
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/28
- IPC: H01L23/28 ; H01L23/29 ; H01L23/00 ; H01L23/31 ; H01L23/538 ; H01L25/10 ; H01L21/56
Abstract:
Apparatus, and methods of manufacture thereof, in which a molding compound is formed between spaced apart microelectronic devices. The molding compound comprises micro-filler elements. No boundary of any of the micro-filler elements is substantially parallel to a substantially planar surface of the molding compound, or to a substantially planar surface of any of the microelectronic devices.
Public/Granted literature
- US20180190555A1 Molding Structure for Wafer Level Package Public/Granted day:2018-07-05
Information query
IPC分类:
