Invention Grant
- Patent Title: Bonded semiconductor wafer and method for manufacturing bonded semiconductor wafer
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Application No.: US15553008Application Date: 2016-02-05
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Publication No.: US10283401B2Publication Date: 2019-05-07
- Inventor: Osamu Ishikawa , Masahiro Kato
- Applicant: SHIN-ETSU HANDOTAI CO., LTD.
- Applicant Address: JP Tokyo
- Assignee: SHIN-ETSU HANDOTAI CO., LTD.
- Current Assignee: SHIN-ETSU HANDOTAI CO., LTD.
- Current Assignee Address: JP Tokyo
- Agency: Oliff PLC
- Priority: JP2015-045284 20150306
- International Application: PCT/JP2016/000594 WO 20160205
- International Announcement: WO2016/143252 WO 20160915
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/762 ; H01L27/12 ; H01L21/265 ; H01L23/00 ; H01L21/322

Abstract:
A bonded semiconductor wafer provided with a single crystal silicon layer on a main surface, wherein the bonded semiconductor wafer has a base wafer composed of a silicon single crystal, and the bonded semiconductor wafer has a first dielectric layer, a polycrystalline silicon layer, a second dielectric layer, and the single crystal silicon layer above the base wafer in this order, with a bonding plane lying between the polycrystalline silicon layer and the second dielectric layer; and wherein a carrier trap layer is formed between the base wafer and the dielectric layer. This provides a bonded semiconductor wafer of a trap-rich type SOI substrate wherein the base wafer can be prevented from lowering the specific resistance due to impurities and influence of electric charge in the BOX oxide film, distortion of radio-frequency fundamental signals and crosstalk signals from one circuit to another circuit are decreased, and the mass-productivity is excellent.
Public/Granted literature
- US20180033681A1 BONDED SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING BONDED SEMICONDUCTOR WAFER Public/Granted day:2018-02-01
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