Invention Grant
- Patent Title: Integrated circuit package pad and methods of forming
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Application No.: US15805683Application Date: 2017-11-07
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Publication No.: US10283375B2Publication Date: 2019-05-07
- Inventor: Hsien-Wei Chen , Chen-Hua Yu , Chi-Hsi Wu , Der-Chyang Yeh , An-Jhih Su , Wei-Yu Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L21/56 ; H01L23/31 ; H01L23/498 ; H01L25/00 ; H01L23/00 ; H01L25/10 ; H01L25/065 ; H01L23/538
Abstract:
A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.
Public/Granted literature
- US20180061668A1 Integrated Circuit Package Pad and Methods of Forming Public/Granted day:2018-03-01
Information query
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