Invention Grant
- Patent Title: Method of forming fine line patterns of semiconductor devices
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Application No.: US15680186Application Date: 2017-08-17
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Publication No.: US10283362B2Publication Date: 2019-05-07
- Inventor: Shing-Yih Shih
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: CKC & Partners Co., LLC
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/033 ; H01L21/02

Abstract:
A method of forming fine line patterns of semiconductor devices includes: forming a plurality of lower linear core structures on at least one lower hard mask layer disposed on a target layer; forming a spacer layer on the hard mask layer to cover the lower linear core structures; forming an upper hard mask layer on the spacer layer; thinning the upper hard mask layer to expose potions of the spacer layer; and removing the exposed portions of the spacer layer to form a plurality of line patterns on the lower hard mask layer.
Public/Granted literature
- US20190057871A1 METHOD OF FORMING FINE LINE PATTERNS OF SEMICONDUCTOR DEVICES Public/Granted day:2019-02-21
Information query
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