Invention Grant
- Patent Title: Stacked die semiconductor device with separate bit line and bit line bar interconnect structures
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Application No.: US14673108Application Date: 2015-03-30
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Publication No.: US10283171B2Publication Date: 2019-05-07
- Inventor: Shyh-An Chi
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: G11C5/02
- IPC: G11C5/02 ; G11C5/06
Abstract:
An apparatus includes a first tier, a second tier and a memory. The second tier is vertically stacked on the first tier. The memory includes a column of memory bit cells. A first portion of the column of memory bit cells is on the first tier. A second portion of the column of memory bit cells is on the second tier.
Public/Granted literature
- US20160293227A1 STACKED DIE SEMICONDUCTOR DEVICE WITH INTERCONNECT STRUCTURE Public/Granted day:2016-10-06
Information query
