Invention Grant
- Patent Title: Dual gate array substrate, testing method, display panel and display apparatus
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Application No.: US15534526Application Date: 2016-06-27
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Publication No.: US10283027B2Publication Date: 2019-05-07
- Inventor: Xinfeng Ren
- Applicant: BOE TECHNOLOGY GROUP CO., LTD. , HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
- Applicant Address: CN Beijing CN Anhui
- Assignee: BOE TECHNOLOGY GROUP CO., LTD.,HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
- Current Assignee: BOE TECHNOLOGY GROUP CO., LTD.,HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
- Current Assignee Address: CN Beijing CN Anhui
- Agency: Calfee, Halter & Griswold LLP
- Priority: CN201610173093 20160324
- International Application: PCT/CN2016/087237 WO 20160627
- International Announcement: WO2017/161722 WO 20170928
- Main IPC: G09G3/00
- IPC: G09G3/00 ; G01R31/28 ; H01L27/12 ; H01L27/28 ; H01L29/786
Abstract:
A dual gate array substrate is disclosed. In two vertically adjacent pixel pairs, two pixel units in each of the pixel pairs are connected to the same data line of the two adjacent data lines respectively, and two adjacent pixel units in the two pixel pairs in an extending direction of the data line are connected to different data lines in the two adjacent data lines respectively; in two adjacent pixel pairs in an extending direction of any set of the dual gate lines, a data line connected to two pixel units in one pixel pair is different from but adjacent to a data line connected to two pixel units in the other pixel pair; and two adjacent pixel units in the extending direction of the data line are connected to their respective adjacent gate lines transmitting different scan signals respectively.
Public/Granted literature
- US20180061291A1 DUAL GATE ARRAY SUBSTRATE, TESTING METHOD, DISPLAY PANEL AND DISPLAY APPARATUS Public/Granted day:2018-03-01
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