Invention Grant
- Patent Title: Methods of forming an array of cross point memory cells
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Application No.: US15827059Application Date: 2017-11-30
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Publication No.: US10263183B2Publication Date: 2019-04-16
- Inventor: Scott E. Sills , Durai Vishak Nirmal Ramaswamy
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L27/24 ; H01L27/11 ; G11C11/22 ; H01L27/11507

Abstract:
A method of forming an array of cross point memory cells comprises forming spaced conductive lower electrode pillars for individual of the memory cells being formed along and elevationally over spaced lower first lines. Walls cross elevationally over the first lines and between the electrode pillars that are along the first lines. The electrode pillars and walls form spaced openings between the first lines. The openings are lined with programmable material of the memory cells being formed to less-than-fill the openings with the programmable material. Conductive upper electrode material is formed over the programmable material within remaining volume of the openings and spaced upper second lines are formed which cross the first lines elevationally over the conductive upper electrode material that is within the openings. A select device is between the lower electrode pillar and the underlying first line or is between the conductive upper electrode material and the overlying second line for the individual memory cells. Aspects of the invention include an array of cross point memory cells independent of method of manufacture.
Public/Granted literature
- US20180090679A1 Methods Of Forming An Array Of Cross Point Memory Cells Public/Granted day:2018-03-29
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