Invention Grant
- Patent Title: Semiconductor integrated circuit device comprising MISFETs in SOI and bulk substrate regions
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Application No.: US16040305Application Date: 2018-07-19
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Publication No.: US10263012B2Publication Date: 2019-04-16
- Inventor: Hideki Makiyama , Yoshiki Yamamoto
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2011-223666 20111011
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L21/762 ; H01L21/84 ; H01L29/66 ; H01L29/06 ; H01L29/423 ; H01L21/8238
Abstract:
The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.
Public/Granted literature
- US20180350844A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE COMPRISING MISFETS IN SOI AND BULK SUBSTRATE REGIONS Public/Granted day:2018-12-06
Information query
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