Invention Grant
- Patent Title: Method of manufacturing semiconductor device including an n type semiconductor region formed in a p type semiconductor layer
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Application No.: US15456269Application Date: 2017-03-10
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Publication No.: US10256323B2Publication Date: 2019-04-09
- Inventor: Nariaki Tanaka , Tohru Oka
- Applicant: Toyoda Gosei Co., Ltd.
- Applicant Address: JP Kiyosu-Shi, Aichi-Ken
- Assignee: TOYODA GOSEI CO., LTD.
- Current Assignee: TOYODA GOSEI CO., LTD.
- Current Assignee Address: JP Kiyosu-Shi, Aichi-Ken
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2016-059904 20160324
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/02 ; H01L21/285 ; H01L21/324 ; H01L29/10 ; H01L29/20 ; H01L29/423 ; H01L29/78 ; H01L21/265

Abstract:
A technique of improving the breakdown voltage of a semiconductor device is provided. There is provided a method of manufacturing a semiconductor device comprising a process of forming a p-type semiconductor layer that contains a p-type impurity and has a dislocation density of not higher than 1.0×107 cm−2, on an n-type semiconductor layer that contains an n-type impurity and has a dislocation density of not higher than 1.0×107 cm−2; an n-type semiconductor region forming process of forming an n-type semiconductor region in at least part of the p-type semiconductor layer by ion-implanting an n-type impurity into the p-type semiconductor layer and performing heat treatment to activate the ion-implanted n-type impurity; and a process of forming a trench that is recessed to pass through the p-type semiconductor layer and reach the n-type semiconductor layer. In the n-type semiconductor region forming process, a p-type impurity diffusion region in which the p-type impurity contained in the p-type semiconductor layer is diffused is formed in at least part of the n-type semiconductor layer that is located below the n-type semiconductor region.
Public/Granted literature
- US20170278950A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE Public/Granted day:2017-09-28
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