Invention Grant
- Patent Title: Self-aligned trench isolation in integrated circuits
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Application No.: US15802721Application Date: 2017-11-03
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Publication No.: US10256137B2Publication Date: 2019-04-09
- Inventor: Ching-Huang Lu , Lei Xue , Kenichi Ohtsuka , Simon Siu-Sing Chan , Rinji Sugino
- Applicant: Cypress Semiconductor Corporation
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/8234 ; H01L29/06 ; H01L29/66 ; H01L29/788 ; H01L29/792 ; H01L27/11521 ; H01L27/11568

Abstract:
An A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. The self-aligned placement of the trench provides electrical isolation between the first and second devices and allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.
Public/Granted literature
- US20180166323A1 SELF-ALIGNED TRENCH ISOLATION IN INTEGRATED CIRCUITS Public/Granted day:2018-06-14
Information query
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