Invention Grant
- Patent Title: Method and apparatus of a fully-pipelined layered LDPC decoder
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Application No.: US15011252Application Date: 2016-01-29
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Publication No.: US10250280B2Publication Date: 2019-04-02
- Inventor: Bo Xia , Ricky Lap Kei Cheung , Bo Lu
- Applicant: Tensorcom, Inc.
- Applicant Address: US CA Culver City
- Assignee: TensorCom, Inc.
- Current Assignee: TensorCom, Inc.
- Current Assignee Address: US CA Culver City
- Agency: Mintz Levin Cohn Ferris Glovsky and Popeo, P.C.
- Main IPC: H03M13/11
- IPC: H03M13/11

Abstract:
Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.
Public/Granted literature
- US20160173131A1 Method and Apparatus of a Fully-Pipelined Layered LDPC Decoder Public/Granted day:2016-06-16
Information query
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