A voltage detection circuit includes two detection capacitors, which are paired and configured differentially, first to third detection switches, a drive part, a minimum selector and a maximum selector. The first detection switch is formed of a pMOS transistor, which opens and closes a path between one of the detection capacitors and an input node. The second detection switch is formed of an nMOS transistor, which opens and closes a path between the other of the detection capacitors and an input node. The third detection switch is formed of a series circuit of a pMOS transistor and an nMOS transistor, which open and close a path between two detection capacitors. The driving part turns on and off complementarily between the first and second switches and the third detection switch. The minimum selector applies a lower one of voltages of the input nodes as a substrate potential of the nMOS transistor. The maximum selector applies a higher one of the voltages of the input nodes as a substrate potential of the pMOS transistor.