Invention Grant
- Patent Title: Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors
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Application No.: US15938367Application Date: 2018-03-28
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Publication No.: US10249762B2Publication Date: 2019-04-02
- Inventor: Marc A. Bergendahl , Kangguo Cheng , Eric R. Miller , John R. Sporre , Sean Teehan
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Fleit Gibbons Gutman Bongini Bianco PL
- Agent Thomas S. Grzesik
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/786 ; H01L21/768 ; H01L29/06 ; H01L29/08 ; H01L27/088 ; H01L21/8234 ; H01L29/423 ; B82Y10/00 ; H01L29/40 ; H01L29/417 ; H01L29/775 ; H01L29/78

Abstract:
A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.
Public/Granted literature
- US20180219101A1 VERTICALLY ALIGNED NANOWIRE CHANNELS WITH SOURCE/DRAIN INTERCONNECTS FOR NANOSHEET TRANSISTORS Public/Granted day:2018-08-02
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