• Patent Title: Solid-state imaging device and electronic apparatus with multiple layers of signal lines and interconnect lines
  • Application No.: US15110573
    Application Date: 2015-01-09
  • Publication No.: US10249670B2
    Publication Date: 2019-04-02
  • Inventor: Hiroaki Seko
  • Applicant: SONY CORPORATION
  • Applicant Address: JP Tokyo
  • Assignee: Sony Corporation
  • Current Assignee: Sony Corporation
  • Current Assignee Address: JP Tokyo
  • Agency: Sheridan Ross P.C.
  • Priority: JP2014-009182 20140122
  • International Application: PCT/JP2015/050435 WO 20150109
  • International Announcement: WO2015/111446 WO 20150730
  • Main IPC: H01L23/522
  • IPC: H01L23/522 H01L27/146
Solid-state imaging device and electronic apparatus with multiple layers of signal lines and interconnect lines
Abstract:
The present disclosure relates to a solid-state imaging device that can reduce crosstalk interference, and to an electronic apparatus. In the upper chip, VSLs, VSLs, and control lines are stacked in this order from the bottom. That is, in the stacked solid-state imaging device, the control lines are laid out in the uppermost layer of the upper chip. In this structure, the influence of a lower chip on the two sets of VSLs can be shielded by the control lines. The present disclosure can be applied to CMOS solid-state imaging devices to be used in electronic apparatuses, such as a camera apparatus.
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